Invited Keynote Lecture
The supercomputer “Fugaku” is the first exascale system with 1 EFLOPS(SP) peak performance, which is operated since March 2021 in R-CCS, Japan. Fugaku is an ultra-scale “general-purpose” manycore-based system with 158,976 nodes, 7.6M cores in total. Fugaku was designed in application-oriented and power-efficient approach to accommodate variety kinds of large-scale applications. Recently, as several supercomputers such as ORNL Frontier supercomputer in US are reaching to exascale, interests in the next of exascale systems are increased. Although it will be very difficult to reach to “Zetta” FLOPS, the system will be heterogenous and integrated with several different configurations for the next of exascale as “Zetta”-scale. Acceleration technologies including FPGAs and reconfigurable devices are promising and inevitable to challenge the “Zetta” scale computing. In this talk, the overview and features of “Fugaku” system will be presented, followed by the challenges for “Zetta”-scale computing.
Mitsuhisa Sato received his undergraduate degree in 1982 from the Department of Information Science, School of Science, the University of Tokyo, and continued his study at the Graduate School of Science, the University of Tokyo, after which he joined the GOTO Quantum Magneto Flux Logic Project at the Research Development Corporation of Japan. In 1991 he joined the Electrotechnical Laboratory of the Ministry of International Trade and Industry (MITI), and from 1996 headed the Parallel and Distributed System Performance Laboratory of the Real World Computing Partnership. From 2001 to 2015 he served as Professor in the Graduate School of Systems and Information Engineering, University of Tsukuba, and Director of the Center for Computational Sciences from 2007 to 2012.
At the RIKEN Advanced Institute for Computational Science (AICS) he led the Programming Environment Research Team from 2010, and since 2014 has been appointed to deputy project leader for the Flagship 2020 Project at AICS (now R-CCS). He serves as Deputy Director of R-CCS since fiscal year 2018. He is also Professor (Cooperative Graduate School Program), Tsukuba University; Professor Emeritus, the University of Tsukuba; and Fellow of the Information Processing Society of Japan. His research interests include: parallel processing architecture; programming models, languages, and compilers; computer performance evaluation technology.
An Agile Hardware-Software Co-design for NAS-Optimized Deep Learning Networks
Computing on edge is one of approaches to reach singular intelligence point with low carbon cost. The recent network architecture search (NAS) has provided a convenient means to find optimized deep learning networks for edge computing by searching bitwidth, sparsity and rank etc., which usually results in a mixed-complexity network at each layer. However, there is no hardware to support computing mixed-complexity networks on edge. This talk will show an agile hardware-software co-design for NAS-optimized deep learning networks. It mainly shows details on how to build a mixed- bitwidth/sparsity vector systolic accelerator with high energy efficiency. Recent works on tensor systolic and computing-in-memory architectures will be also mentioned briefly.
Prof. Hao Yu obtained his PhD degree from UCLA in 2007, and was the founding vice dean at school of microelectronics (SUSTech) since 2017. He is the director of MOE National Engineering Center, winner of WU’s National AI Awards in 2019/2020. He has published > 10 books, >100 journals as well as > 250 conferences in IEEE/ACM publishing, including best papers of ACM- TODAES in 2010 and IEEE-BioCAS in 2018. He was the Distinguished Lecturer of IEEE-CAS, Associate Editors of IEEE-TBioCAS, ACM-TEC, Elsevier-(Microelectronics， VLSI Integration), and Scientific Reports. He was also TPC members of many IEEE/ACM conferences (CICC/ASSCC/ICCAD/DAC/DATE), with 3 invited keynotes and >50 invited talks. He is the senior member of IEEE.
Invited Industrial Talk
Atom switch technology for energy efficient electronics
Abstract: Atom switch is a two-terminal resistive switch based on Cu precipitation in the polymer solid-electrolyte and is characterized by non-volatility, adjustable ON/OFF conductance ratio, radiation tolerance, and small footprint. Atom switch advantageously applies to both routing switch in FPGA and memory cell in non-volatile memory (NVM), resulting in high energy efficient electronics. The ON conductance and the cycling endurance, which are in a trade-off relationship, are controlled by programming current to meet the requirements of its application. Atom switch provides a large ON/OFF conductance ratio for FPGA. It also provides a 100k-cycle endurance for NVM applications. Nonvolatile SoC-FPGA solution with low power consumption is achieved by multi-usage atom switch.
Toshitsugu Sakamoto received the B.S., M.S., and Ph.D. degrees in electrical engineering from Osaka University. After joining the NEC Corporation in 1991, he worked on nanometer-scale devices as hot electron transistors and on single electron devices. He is working on the solid-electrolyte device and circuits. From 1999 to 2000, he was a visiting researcher with California Institute of Technology, Pasadena.